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brief RK3026 high performance and low-power processor for digital media application - 1 - RK3026 brief revision 1 . 1 public version august 2013
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brief RK3026 high performance and low-power processor for digital media application - 3 - content content ................................................................................................................................................................ - 3 - 5daov i introduction ...................................................................................................................... - 5 - iri overview ..................................................................................................................................... - 5 - irs features ...................................................................................................................................... - 5 - irl block diagram .......................................................................................................................... - 15 -
brief RK3026 high performance and low-power processor for digital media application - 4 - warranty disclaimer rockchip electronics co.,ltd make s no warranty, representation or guarantee (expressed, implied, statutory, or otherwise) by or with respect to anything in this document, and shall not be liable for any implied warranties of non - infringement, merchantab i lity or fitness for a particular purpose or for any indirect, special or consequential damages. information furnished is believed to be accurate and reliable. however, rockchip electronics co.,ltd assumes no responsibility for the consequenc e s of use of such information or for any infringement of patents or other rights of third parties that may result from its use. rockchip electronics co.,ltd s products are not designed, intended, or authorized for us ing as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the rockchip electronics co.,ltd s product could create a situation where personal injury or death may occur, should buyer purchase or use rockchip electronics co.,ltd s products for any such unintended or unauthorized ap p licat i on, buyer s shall indemnify and hold rockchip electronics co.,ltd and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that rockchip electronics co.,ltd was negligent regarding the design or manufacture of the part. copyright and patent right information in this document is provided solely to enable system and software implementers to use rockchip electronics co.,ltd s products. the r e are no express ed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. rockchip electronics co.,ltd does not convey any license under its patent rights nor the rights of others. trademarks rockchip and rockchip tm logo and the name of rockchip electronics co.,ltd s products are trademarks of rockchip electronics co.,ltd. and are exclusively owned by rockchip electronics co.,ltd. references to other companies and their products use trademarks owned by the respective companies and are for reference purpose only. confidentiality the information contained herein (including any attachments) is confidential. the recipient hereby acknowledges the confidentiality of this document, and except for the specific purpose, this document shall not be disclosed to any third party. reverse engineering or disassembly is prohibited. rockchip electronics co.,ltd. reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to undate this documentation to reflect such changes. copyright ? 201 3 rockchip electronics co.,ltd. all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of rockchip electronics co.,ltd. rockchip electronics co.,ltd. no, 18 building, a district, fuzhou software park, fujian, china tel: +86-591-83991906 fax:+86-591-83951833 www .rock-chips.com
brief RK3026 high performance and low-power processor for digital media application - 5 - chapter 1 introduction 1.1 overview RK3026 is a low power, high performance processor solution for tablet, and other digital multimedia applications, and integrates dual-core cortex-a9 with separately neon and fpu coprocessor ,and also with 256kb l2 cache . many embedded powerful hardware engines provide optimized performance for high-end application. RK3026 supports almost full-format video decoder by 1080p@60fps, also support h.264/mvc/vp8 encoder by 1080p@30fps, high-quality jpeg encoder/decoder and special image preprocessor and postprocessor . embedded 3d gpu makes RK3026 completely compatible with opengl es1.1 and 2.0, openvg 1.1 etc . special 2d hardware engine with mmu will maximize display performance. RK3026 has high-performance external memory interface(ddr3/lvddr3) capable of sustaining demanding memory bandwidths, also provides a complete set of peripheral interface to support very flexible applications as follows : ? support 8bits async nand flash , sync toggle nand flash, lba nand flash and sync onfi nand flash, 4 banks,all embedded up to 60bits hardware ecc ? 2 ranks, 1gb memory space, 16bits ddr3- 1066 , lvddr3- 1066 ? support 8bits emmc ? one -channel s sd/mmc interface to support 4bits mmc4.41, sd3.0 or sdio3.0 ? 4-layers tft lcd controller, 24 bits data, 1920x1080 maximum display size ? 18/24 bits lvds output , and c omply with the standard tia/eia-644-a lvds ? one- channel, 8bits ccir656 interface and 8bits raw data interface ? one i2s/pcm interface ? one usb otg 2.0 and one usb host2.0 interface ? 3 x i2c, 1 xuart with hardware flow-control , 1x spi , 2 x pwm ? audio codec with mon o microphone interfac e 1.2 features 1.2.1 microprocessor ? dual-core arm cortex-a9 processor is a high-performance, low-power, cached application processor ? full implementation of the arm architecture v7-a instruction set, arm neon advanced simd (single instruction, multiple data) support for accelerated media and signal processing computation ? superscalar, variable length, out-of-order pipeline with dynamic branch prediction, 8-stage pipeline ? include vfpv3 hardware to support single and double-precision add, subtract, divide, multiply and accumulate, and square root operations ? integrated timer and watchdog timer in cpu ? integrated 32kb l1 instruction cache , 32kb l1 data cache, 4-way set associative ? 256kb unified l2 cache ? coresight debug solution ? invasive debug ? one isolated voltage domain to support dvfs ? maximum frequency can be up to 1.0ghz@1.1 v , 25 c
brief RK3026 high performance and low-power processor for digital media application - 6 - 1.2.2 memory organization ? internal on-chip memory ? 16kb bootrom ? 8kb internal sram ? external off-chip memory ? ddr3- 1066 , 16bits data width, 2 ranks, 1gb (max) address space per rank ? lvddr3- 1066 , 16bits data width, 2 ranks, 1gb (max) address space per rank ? async/ sync toggle/ sync onfi nand flash(include lba nand), 8bits data width, 4 banks 1.2.3 internal memory ? internal bootrom ? size : 1 6 kb ? support system boot from the following device : ? 8bits async nand flash ? spi interface ? emmc interface ? sdmmc interface ? support system code download by the following interface: ? usb otg ? uart 1 ? internal sram ? size : 8kb 1.2.4 external memory or storage device ? dynamic memory interface (ddr3/lvddr3) ? compatible with jedec standard ddr3/ lvddr3 sdram ? data rates of up to 1 0 66 mbps( 533 mhz) for ddr3/lvddr3 ? support up to 2 ranks (chip selects), maximum 1gb address space per rank ? advanced command reordering and scheduling to maximize bus utilization ? low power modes, such as power-down and self-refresh for ddr3/ lvddr3 sdram; ? compensation for board delays and variable latencies through programmable pipelines ? programmable output and odt impedance with dynamic pvt compensation ? nand flash interface ? support 8bits async/toggle/syncnandflash, up to 4 banks ? support lba nandflash ? 16bits, 24bits, 40bits, 60bits hardware ecc ? for ddr nandflash, support dll bypass and 1/4 or 1/8 clock adjust, maximum clock rate is 66.5mhz ? for async/togglenandflash, support configurable interface timing , maximum data rate is 16bit/cycle ? embedded ahb master interface to do data transfer by dma method ? also support data transfer by ahb slave interface together with external dmac ? emmc interface ? compatible with standard inand interface ? support mmc4.41 protocol ? provide emmc boot sequence to receive boot data from external emmc device ? support combined single fifo(32x32bits) for both transmit and receive operations ? support fifo over-run and under-run prevention by stopping card clock automatically ? support crc generation and error detection
brief RK3026 high performance and low-power processor for digital media application - 7 - ? embedded clock frequency division control to provide programmable baud rate ? support block size from 1 to 65535bytes ? 8bits data bus width ? sd/mmc interface ? compatible with sd 2 .0, mmc ver4.41 ? support combined single fifo(32x32bits) for both transmit and receive operations ? support fifo over-run and under-run prevention by stopping card clock automatically ? support crc generation and error detection ? embedded clock frequency division control to provide programmable baud rate ? support block size from 1 to 65535bytes data bus width is 4bits 1.2.5 system component ? cru (clock & reset unit) ? support clock gating control for individual components inside RK3026 ? support global soft-reset control for whole soc, also individual soft-reset for every components ? support flexible clock solution, including clock source, clock mux, clock frequency division ? one oscillator with 24mhz clock and 4 embedded plls ? timer ? o n-chip 64bits timers with interrupt-based operation ? provide two operation modes: free-running and user-defined count ? support timer work state checkable ? 24mhz/pclk clock input for operating domain, and pclk input for bus interface domain. ? pwm ? o n-chip pwms with interrupt-based operation ? programmable 4-bit pre-scalar from apb bus clock ? embedded 32-bit timer/counter facility ? support single-run or continuous-run pwm mode ? provides reference mode and output various duty-cycle waveform ? watchdog ? 32 bits watchdog counter width ? counter clock is from apb bus clock ? counter counts down from a preset value to 0 to indicate the occurrence of a timeout ? wdt can perform two types of operations when timeout occurs: ? generate a system reset ? first generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset ? programmable reset pulse length ? totally 16 defined-ranges of main timeout period ? bus architecture ? qos function is supported to improve the utility of bus bandwidth ? interrupt controller ? support 3 ppi interrupt source and 96 spi interrupt sources input from different components inside RK3026 ? support 16 softwre-triggered interrupts ? input interrupt level is fixed , only high-level sensitive ? two interrupt output (nfiq and nirq) to per cortex-a9, both are low-level
brief RK3026 high performance and low-power processor for digital media application - 8 - sensitive ? support different interrupt priority for each interrupt source, and they are always software-programmable ? dmac ? linked list dma function is supported to complete scatter-gather transfer ? support data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory ? signals the occurrence of various dma events using the interrupt output signals ? mapping relationship between each channel and different interrupt outputs is software-programmable ? one embedded dma controller inperi system ? dmac features: ? 8 channels totally ? 13 hardware request from peripherals ? 2 interrupt output ? not support trustzone technology 1.2.6 video codec ? video decoder ? real-time video decoder of mpeg-1, mpeg-2, mpeg-4,h.263, h.264 , vc-1 , rv , vp6/vp8 , sorenson spark ? error detection and concealment support for all video formats ? output data structure after decoder is ycbcr 4:2:0 semi-planar to have more efficient bus usage, for h.264, ycbcr 4:0:0(monochrome) is also supported ? minimum image size is 48x48 for all video formats ? h.264 up to hp level 4.2 : 1080p@60fps (1920x108 0 ) ? mpeg-4 up to asp level 5 : 1080p@60fps (1920x108 0 ) ? mpeg-2 up to mp : 1080p@60fps (1920x108 0 ) ? mpeg-1 up to mp : 1080p@60fps (1920x108 0 ) ? h.263 : 576p@60fps (720x576) ? sorenson spark : 1080p@60fps (1920x108 0 ) ? vc-1 up to ap level 3 : 1080p@30fps (1920x108 0 ) ? rv8/rv9/rv10 : 1080p@60fps (1920x108 0 ) ? vp6/vp8 : 1080p@60fps (1920x108 0 ) ? for h.264, image cropping not supported ? for mpeg-4,gmc(global motion compensation) not supported ? for vc-1, upscaling and range mapping are supported in image post-processor ? for mpeg-4 sp/h.263/sorenson spark, using a modified h.264 in-loop filter to implement deblocking filter in post-processor unit ? video encoder ? encoder only for h.264 ( bp@level4.0 , mp@level4.0,hp@level4.0 ) standard ? only support i and p slices, not b slices ? entropy encoding is cavlc in bp and cabac in mp ? support error resilience based on constrained intra prediction and slices ? maximum mv length is +/- 14 pixels in vertical direction and +/-30 pixels in horizontal direction ? motion vector pixel accuracy is up to 1/4 pixels in 720p resolution and 1/2 pixels in 1080p resolution ? 12 intra prediction modes ? number of reference frames is 1 ? maximum number of slice groups is 1 ? input data format : ? ycbcr 4:2:0 planar ? ycbcr 4:2:0 semi-planar
brief RK3026 high performance and low-power processor for digital media application - 9 - ? ycbycr 4:2:2 ? cbycry 4:2:2 interleaved ? rgb444 and bgr444 ? rgb555 and bgr555 ? rgb565 and bgr565 ? rgb888 and brg888 ? rgb101010 and brg101010 ? output data format : h.264 byte unit stream and h.264 nal unit stream ? image size is from 96x96 to 1920x108 0 (full hd) ? maximum frame rate is up to 30fps@1920x1080 ? bit rate supported is from 10kbps to 20mbps 1.2.7 jpeg codec ? jpeg decoder ? input jpeg file : ycbcr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 sampling formats ? output raw image : ycbcr 4:0:0, 4:2:0, 4:2:2, 4:4:0, 4:1:1 and 4:4:4 semi-planar ? decoder size is from 48x48 to 8176x8176(66.8mpixels) ? maximum data rate is up to 76million pixels per second ? jpeg encoder ? input raw image : ? ycbcr 4:2:0 planar ? ycbcr 4:2:0 semi-planar ? ycbycr 4:2:2 ? cbycry 4:2:2 interleaved ? rgb444 and bgr444 ? rgb555 and bgr555 ? rgb565 and bgr565 ? rgb888 and brg888 ? rgb101010 and brg101010 ? output jpeg file : jfif file format 1.02 or non-progressive jpeg ? encoder image size up to 8192x8192(64million pixels) from 96x32 ? maximum data rate up to 90million pixels per second 1.2.8 image enhancement(inside video encoder/decoder in on2) ? image pre-processor(embedded inside video encoder) ? only used together with hd video encoder inside RK3026 , not support stand-alone mode ? provides rgb to ycbcr 4:2:0 color space conversion, compatible with bt.601 , bt.709 or user defined coefficients ? provides ycbcr4:2:2 to ycbcr4:2:0 color space conversion ? support cropping operation from 8192x8192 to any supported encoding size ? support rotation with 90 or 270 degrees ? video stabilization(embedded inside video encoder) ? work in combined mode with hd video encoder inside rk30xx and stand-alone mode ? adaptive motion compensation filter ? support scene detection from video sequence, encodes key frame when scene change noticed ? image post-processor(embedded inside video decoder) ? combined with hd video decoder and jpeg decoder, post-processor can read input data directly from decoder output to reduce bus bandwidth
brief RK3026 high performance and low-power processor for digital media application - 10 - ? also work as a stand-alone mode, its input data is from a camera interface or other image data stored in external memory ? input data format : ? any format generated by video decoder in combined mode ? ycbcr 4:2:0 semi-planar ? ycbcr 4:2:0 planar ? ycbycr 4:2:2 ? ycrycb 4:2:2 ? cbycry 4:2:2 ? crycby 4:2:2 ? ouput data format: ? ycbcr 4:2:0 semi-planar ? ycbycr 4:2:2 ? ycrycb 4:2:2 ? cbycry 4:2:2 ? crycby 4:2:2 ? fully configurable argb channel lengths and locations inside 32bits, such as argb8888,rgb565,argb4444 etc. ? input image size: ? combined mode : from 48x48 to 8176x8176 (66.8mpixels) ? stand-alone mode : width from 48 to 8176,height from 48 to 8176, and maximum size limited to 16.7mpixels ? step size is 16 pixels ? output image size: from 16x16 to 1920x1088 (horizontal step size 8,vertical step size 2) ? support image up-scaling : ? bicubic polynomial interpolation with a four-tap horizontal kernel and a two-tap vertical kernel ? arbitrary non-integer scaling ratio separately for both dimensions ? maximum output width is 3x input width ? maximum output height is 3x input height ? support image down-scaling: ? arbitrary non-integer scaling ratio separately for both dimensions ? unlimited down-scaling ratio ? support yuv to rgb color conversioin, compatible with bt.601-5, bt.709 and user definable conversion coefficient ? support dithering (2x2 ordered spatial dithering for 4,5,6bit rgb channel precision ? support programmable alpha channel and alpha blending operation with the following overlay input formats: ? 8bit alpha +yuv444, big endian channel order with ayuv8888 ? 8bit alpha +24bit rgb, big endian channel order with argb8888 ? support deinterlacing with conditional spatial deinterlace filtering, only compatible with yuv420 input format ? support rgb image contrast / brightness / color saturation adjustment ? support image cropping & digital zoom only for jpeg or stand-alone mode ? support picture in pcture ? support image rotation (horizontal flip, vertical flip, rotation 90,180 or 270 degrees) 1.2.9 image enhancement(new iep lite module) ? image format support ? input data: xrgb/rgb565/yuv420/yuv422 ? output data: argb/rgb565/yuv420/yuv422 ? argb/xrgb/rgb565/yuv swap ? uv sp/p
brief RK3026 high performance and low-power processor for digital media application - 11 - ? bt601_l/bt601_f/bt709_l/bt709_f color space conversion ? rgb dither up/down ? yuv up/down sampling ? max source image resolution: 8192x8192 ? max scaled image resolution: 4096x4096 ? yuv enhancement &denoise ? hue, saturation, brightness, contrast adjustment ? rgb enhancement &denoise ? contrast enhancement ? color enhancement ? gamma adjustment ? high quality scale ? averaging filter down-scaling ? bi-cubic up-scaling ? arbitrary non-integer horizontal & vertical scaling ratio range from 1/16 to 16 ? de-interlace ? 3x5 y motion detection matrix ? source width up to 1920 ? configed high frequency de-interlace ? i4o2 (input 4 field,output 2 frame) /i4o1b/i4o1t/i2o1b/i2o1t mode ? interface ? configed direct path to lcdc if source width no more than 1920 ? 32bit ahb bus slave ? 64bit axi bus master ? combined interrupt output 1.2.10 graphics engine ? 3d graphics engine : ? high performance opengl es1.1 and 2.0, openvg1.1 etc. ? embedded 4shader cores with shared hierarchical tiler ? separate vertex(geometry) and fragment(pixel) processing for maximum parallel throughput ? provide mmu and l2 cache with 32kb size ? triangle rate : 30m triangles/s ? pixel rate: 300 pixels/s @ 150mhz ? 2d graphics engine(rga module) : ? pixel rate: 300m pixel/s without scale, 150m pixel/s with bilinear scale, 66.5m pixel/s with bicubic scale. ? bit blit with strength blit, simple blit and filter blit ? color fill with gradient fill, and pattern fill ? line drawing with anti-aliasing and specified width ? high-performance stretch and shrink ? monochrome expansion for text rendering ? rop2, rop3, rop4 full alpha blending and transparency ? alpha blending modes including java 2 porter-duff compositing blending rules , chroma key, and pattern mask ? 8k x 8k raster 2d coordinate system ? arbitrary degrees rotation with anti-aliasing on every 2d primitive ? programmable bicubic filter to support image scaling ? blending, scaling and rotation are supported in one pass for stretch blit ? source formats : ? abgr8888, xbgr888, argb8888, xrgb888
brief RK3026 high performance and low-power processor for digital media application - 12 - ? rgb888, rgb565 ? rgba5551, rgba4444 ? yuv420 planar, yuv420 semi-planar ? yuv422 planar, yuv422 semi-planar ? bpp8, bpp4, bpp2, bpp1 ? destination formats : ? abgr8888, xbgr888, argb8888, xrgb888 ? rgb888, rgb565 ? rgba5551, rgba4444 ? yuv420 planar, yuv420 semi-planar only in filter and pre-scale mode ? yuv422 planar, yuv422 semi-planar only in filter and pre-scale mode 1.2.11 video in/out ? camera interface ? support up to 5m pixels ? 8bits ccir656(pal/ntsc) interface ? 8bits raw data interface ? yuv422 data input format with adjustable yuv sequence ? yuv422,yuv420 output format with separately y and uv space ? support picture in picture (pip) ? support image crop with arbitrary windows ? display interface ? support lcd or tft interfaces up to 1920x1080 ? parallel rgb lcd interface : rgb666(18bits) ,rgb565(15bits) ? mcu lcd interface: i-8080, hold/auto/bypass modes ? tv interface: itu-r bt.656(8-bit, 480i/576i/1080i) ? max output resolution 1920x1080 ? 4 display layers : ? one background layer with programmable 24bits color ? one video layer (win0) ? rgb888, argb888, rgb565, ycbcr422, ycbcr420, ycbcr444 ? maximum resolution is 1920x1080,support virtual display ? 1/8 to 8 scaling up/down engine with arbitrary non-integer ratio ? 256 level alpha blending ? support transparency color key ? 3d display support ? direct path support ? one video layer (win1) ? rgb888, argb888, rgb565, 1/2/4/8bpp ? support virtual display ? 256 level alpha blending ( pre-multiplied alpha support) ? support transparency color key ? direct path support ? hardware cursor(win3) ? 2bpp , two transparent modes ? support two size: 32x32 and 64x64 ? 16 level alpha blending ? win0 and win1 layer overlay exchangeable ? 3 x 256 x 8 bits display luts ? support color space conversion : yuv2rgb(rec601-mpeg/rec601-jpeg/rec709) and rgb2yuv ? deflicker support for interlace output ? support replication(16bits to 24bits) and dithering(24bits to 16bits/ 18bits) operation
brief RK3026 high performance and low-power processor for digital media application - 13 - ? blank and blank display ? standby mode ? support non-scaler and scaler output(max up to 1024x768) ? lvds interface ? 135mhz clock support ? 28:4 data sub_channel compression at data rates up to 945 mbps per channel ? support vga,svga,xga and single pixel sxga ? pll requires no external components ? comply with the standard tia/eia-644-a lvds standard ? support alternative lvds output or lvttl output 1.2.12 audio interface ? i2s/pcm ? audio resolution from 16bits to 32bits ? sample rate up to 192khz ? provides master and slave work mode, software configurable ? support 3 i2s formats (normal , left-justified , right-justified) ? support 4 pcm formats(early , late1 , late2 , late3) ? i2s and pcm cannot be used at the same time ? audio codec ? 18 to 24 bit high order sigma-delta modulation for dac for >93 db snr configurable ? 16 to 18 bit high order sigma-delta modulation for adc for >90 db snr configurable ? digital interpolation and decimation filter integrated ? microphone in and speaker out interface ? on-chip analog post filter and digital filters ? single C ended or differential input and output ? sampling rate of 8khz/12khz/16khz/ 24khz/32khz /48khz/44.1k/96khz ? support 16ohm to 32ohm head phone and speaker phone output ? mono, stereochannel supported ? optional fractional pll available that support 6mhz to 20mhz clock input to any clockoutput that meets 8khz/12khz/16khz/ 24khz/32khz /48khz/44.1k/96khz and 128 time oversampling ratio. 1.2.13 connectivity ? sdio interface ? compatible with sdio 2 .0 protocol ? support fifo over-run and under-run prevention by stopping card clock automatically ? 4bits data bus width ? spi controller ? support serial-master and serial-slave mode, software-configurable ? dma-based or interrupt-based operation ? embedded two 32x16bits fifo for tx and rx operation respectively ? support 2 chip-selects output in serial-master mode ? uartcontroller ? dma-based or interrupt-based operation ? uart0 embeddeds two 64bytes fifo for tx and rx operation respectively ? uart1/uart2 embedded two 32bytes fifo for tx and rx operation respectively ? support 5bit,6bit,7bit,8bit serial data transmit or receive ? standard asynchronous communication bits such as start,stop and parity
brief RK3026 high performance and low-power processor for digital media application - 14 - ? support different input clock for uart operation to get up to 4mbps or other special baud rate ? support non-integer clock divides for baud clock generation ? support auto flow control mode ? i2c controller ? multi-master i2c operation ? support 7bits and 10bits address mode ? software programmable clock frequency and transfer rate up to 400kbit/s in the fast mode ? serial 8bits oriented and bidirectional data transfers can be made at up to 100kbit/s in the standard mode ? gpio ? all of gpios can be used to generate interrupt to cortex-a9 ? all of pullup gpios are software-programmable for pullup resistor or not ? all of pulldown gpios are software-programmable for pulldown resistor or not ? all of gpios are always in input direction in default after power-on-reset ? usb host2.0 ? compatible with usb host2.0 specification ? supports high-speed(480mbps), full-speed(12mbps) and low-speed(1.5mbps) mode ? provides 16 host mode channels ? support periodic out channel in host mode ? usb otg2.0 ? compatible with usb otg2.0 specification ? supports high-speed(480mbps), full-speed(12mbps) and low-speed(1.5mbps) mode ? support up to 9 device mode endpoints in addition to control endpoint 0 ? support up to 6 device mode in endpoints including control endpoint 0 ? endpoints 1/3/5/7 can be used only as data in endpoint ? endpoints 2/4/6 can be used only as data out endpoint ? endpoints 8/9 can be used as data out and in endpoint ? provides 9 host mode channels 1.2.14 others ? sar-adc(successive approximation register) ? 10-bit sar analog-to-digital converter ? sample rate fs is 200khz ? sar-adc clock must be large than 11*fs, recommend is 11*fs ? dnl less than1 lsb , inl less than 2.0 lsb ? power supply is 3.3v ( 10%) for analog interface, power dissipation is less than 900uw ? efuse ? two 256bits (32x8) high-density electrical fuse ? programming condition : vp must be 2.5v( 10%) ? program time is 10us. ? read condition : vp must be 2.5v( 10%) ? provide inactive mode
brief RK3026 high performance and low-power processor for digital media application - 15 - notes : : ddr3/lvddr3 are not used simultaneously as well as async and sync ddrnand flash : actual maximum frame rate will depend on the clock frequency and system bus performance : actual maximum data rate will depend on the clock frequency and jpeg compression rate 1.3 block diagram the following diagram shows the basic block diagram for RK3026. fig. 1 - 1 RK3026 block diagram

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